1. Field of the Invention
The present invention relates to a differential operational amplifier circuit that is employed for use in, for example, a pipelined A/D converter, where the differential operational amplifier corrects a settling error, and relates to a pipelined A/D converter that employs the differential operational amplifier circuit.
2. Description of the Related Art
In these days when analog-digital consolidation system LSIs play great roles with developments in communication systems and video technologies, reductions in power consumptions of analog circuits are major matters of concern. Advancements in semiconductor fine processing technologies have brought developments in performance and integration density of digital circuits and achieved efficient power reductions with lowered power supply voltages. On the other hand, measures against deteriorations in signal to noise ratio (SNR) and so on due to element variations on processes and lowered voltages are necessary although the basic performances of transistors are improved, and this makes it difficult to design analog circuits for obtaining reliable performances.
Typical applications, which need a high-speed A/D converter whose resolution is 8 bits or more and conversion frequency is 10 megahertz to several hundred megahertz, include consumer-oriented image and video equipment such as digital cameras and video cameras, medical imaging systems such as ultrasonic, X-ray and CT appliances, and the front ends of wireless communication apparatuses such as wireless LAN's and portable telephones. In such applications that require high speed and high resolution, a pipelined A/D converter has been widely used. The pipelined A/D converter is a system that obtains the required resolution by performing pipeline-like operation by connecting a sample hold circuit with fundamental operating circuits that perform M-bit (fundamentally one-bit) A/D conversion per stage (multiplication type A/D converter (MDAC: Multiplying Digital-to-Analog Converter)) in a multistage cascade arrangement (See, for example, Non-Patent Documents and Patent Documents 1 and 2).
Prior art documents related to the present invention are as follows:
Patent Document 1: Japanese patent No. JP3597812;
Patent Document 2: Specification of U.S. Pat. No. 6,756,928;
Patent Document 3: Specification of U.S. Pat. No. 5,748,040;
Patent Document 4: Japanese patent laid-open publication No. JP 2005-210635 A;
Patent Document 5: Japanese patent laid-open publication No. JP 2007-274631 A;
Non-Patent Document 1: Carl R. Grace et al., A 12b 80MS/s Pipelined ADC with Bootstrapped Digital Calibration”, 2004 IEEE International Slid-State Circuits Conference (ISSCC) Digest of Technical Papers, No. 25.5, pp. 460-461, February 2004;
Non-Patent Document 2: Boris Murmann et al., “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue amplification”, IEEE Journal of Solid-state Circuits, Vol. 38, No. 12, pp. 2040-2050, December 2003;
Non-Patent Document 3: Echere Iroaga et al., A 12b, 75 MS/s Pipelined ADC Using Incomplete Settling”, 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp. 274-275, June 2006;
Non-Patent Document 4: Echere Iroaga et al., “A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling”, IEEE Journal of Solid-state Circuits, Vol. 42, No. 4, April 2007; and
Non-Patent Document 5: Olaf Stroeble et al., “An 80 MHz 10b Pipeline ADC with Dynamic Range Doubling and Dynamic keference Selection”, 2004 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, No. 25.6, pp. 462-463, February 2004.
Digital correction to ease the required accuracy of the analog circuit by positively using digital techniques improved in performance by scale shrinkage is generally used in the case of capacitor mismatch that is an error factor of a pipelined A/D converter, finite-gain error of an amplifier and so on. A settling error, which is similarly an error factor, disadvantageously increases power consumption as a consequence of an increase in the bias current of an amplifier if it is generally tried to reduce the error. If the settling error itself can be digitally corrected, it can obviate the need for increasing the bias current of the ampler for reducing the settling error, allowing the power consumption to be remarkably reduced. However, since the settling error when a class-A amplifier with a constant current region is employed is nonlinear, there has been a problem of the necessity of a complicated correction circuit.
Prior art settling error correction methods and the problems thereof are described in detail below.
First of all, a settling error nonlinearity correction method is disclosed in the Non-Patent Document 1. According to this method, a bit-pipelined A/D converter of a closed-loop architecture has a circuit to digitally correct the finite-gain error and nonlinearity in the slewing region. When input signal amplitude is large, the nonlinearity generated as a consequence of incomplete settling due to the influence of slewing is corrected by fitting with an even-order function. According to the this method, the incomplete settling is corrected as a second-order nonlinear function, a complicated correction circuit results with the necessity of a digital multiplier or the Me, and this therefore has led to a problem that the method is not suitable for high resolution of 14 bits or more.
Another settling error nonlinearity correction method using an open-loop architecture is disclosed in the Non-Patent Documents 2 to 4. According to this method, a 12-bit pipelined A/D converter that uses the open loop architecture achieves low power consumption by digitally correcting the nonlinearity, device mismatch and incomplete settling. Assuming that RL is the output resistance of an amplifier and CL is load capacitance, then the settling response of the open loop architecture becomes τ=RLCL when the time constant of the circuit is fallen within the operational range of the amplifier. Therefore, the settling response becomes a linear error in the first-order step response. According to this method, odd-order (third and fifth) nonlinearities ascribed to the open loop architecture itself remain and a complicated correction circuit becomes necessary, and this therefore has led to a problem that the method is not suitable for high resolution of 14 bits or more.
Furthermore, an error correction method with dynamic range doubling is disclosed in the Non-Patent Document 5. According to this method, a signal to noise ratio (SNR) is improved by doubling the input amplitude with respect to the amplitude in the A/D converter by adding other two comparators to the first stage of a conventional 1.5-bit/stage pipeline stage, and power consumption is reduced. According to this method, there has been a problem that an increase in the power consumption of the added comparators, an areal increase due to the added sampling capacitance and recovery of dynamic range in the digital region become necessary.